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| ? 2007 microchip technology inc. ds21191p-page 1 24aa128/24lc128/24fc128 device selection table features: ? single supply with operation down to 1.7v for 24aa128/24fc128 devices, 2.5v for 24lc128 devices ? low-power cmos technology: - write current 3 ma, typical - standby current 100 na, typical ? 2-wire serial interface, i 2 c? compatible ? cascadable up to eight devices ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 khz and 400 khz clock compatibility ? 1 mhz clock for fc versions ? page write time 5 ms, typical ? self-timed erase/write cycle ? 64-byte page write buffer 24aa128/24lc128/24fc128 ds21191p-page 2 ? 2007 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins ............................................................................................................................... ....................... 4kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: industrial (i): v cc = +1.7v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions d1 ? a0, a1, a2, scl, sda and wp pins: ???? d2 v ih high-level input voltage 0.7 v cc ?v? d3 v il low-level input voltage ? 0.3 v cc 0.2 v cc v v v cc 2.5v v cc < 2.5v d4 v hys hysteresis of schmitt trigger inputs (sda, scl pins) 0.05 v cc ?vv cc 2.5v (note 1) d5 v ol low-level output voltage ? 0.40 v i ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v d6 i li input leakage current ? 1 av in = v ss or v cc , wp = v ss v in = v ss or v cc , wp = v cc d7 i lo output leakage current ? 1 av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) ?10pfv cc = 5.0v (note 1) t a = 25c, f clk = 1 mhz d9 i cc read operating current ? 400 av cc = 5.5v, scl = 400 khz i cc write ? 3 ma v cc = 5.5v d10 i ccs standby current ? 1 at a = -40c to +85c scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss ?5 at a = -40c to 125c scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss note 1: this parameter is periodically sampled and not 100% tested. ? 2007 microchip technology inc. ds21191p-page 3 24aa128/24lc128/24fc128 table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = +1.7v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions 1f clk clock frequency ? ? ? ? 100 400 400 1000 khz 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 2t high clock high time 4000 600 600 500 ? ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 3t low clock low time 4700 1300 1300 500 ? ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 4t r sda and scl rise time (note 1) ? ? ? 1000 300 300 ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc 5.5v 24fc128 5t f sda and scl fall time (note 1) ? ? 300 100 ns all except, 24fc128 1.7v v cc 5.5v 24fc128 6t hd : sta start condition hold time 4000 600 600 250 ? ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 7t su : sta start condition setup time 4700 600 600 250 ? ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 8t hd : dat data input hold time 0 ? ns (note 2) 9t su : dat data input setup time 250 100 100 ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc 5.5v 24fc128 10 t su : sto stop condition setup time 4000 600 600 250 ? ? ? ? ns 1.7 v v cc < 2.5v 2.5 v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5 v v cc 5.5v 24fc128 11 t su : wp wp setup time 4000 600 600 ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc 5.5v 24fc128 12 t hd : wp wp hold time 4700 1300 1300 ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc 5.5v 24fc128 note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site at www.microchip.com. 24aa128/24lc128/24fc128 ds21191p-page 4 ? 2007 microchip technology inc. figure 1-1: bus timing data 13 t aa output valid from clock (note 2) ? ? ? ? 3500 900 900 400 ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 14 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 1300 500 ? ? ? ? ns 1.7v v cc < 2.5v 2.5v v cc 5.5v 1.7v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 15 t of output fall time from v ih minimum to v il maximum c b 100 pf 10 + 0.1c b 250 250 ns all except, 24fc128 (note 1) 24fc128 (note 1) 16 t sp input filter spike suppression (sda and scl pins) ? 50 ns all except, 24fc128 (notes 1 and 3) 17 t wc write cycle time (byte or page) ?5ms? 18 ? endurance 1,000,000 ? cycles 25c (note 4) table 1-2: ac characteristics (continued) ac characteristics electrical characteristics: industrial (i): v cc = +1.7v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site at www.microchip.com. (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14 ? 2007 microchip technology inc. ds21191p-page 5 24aa128/24lc128/24fc128 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 a0, a1, a2 chip address inputs the a0, a1 and a2 inputs are used by the 24xx128 for multiple device operations. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. for the msop package only, pins a0 and a1 are not connected. up to eight devices (two for the msop package) may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v cc or v ss . in most applications, the chip address inputs a0, a1 and a2 are hard-wired to logic ? 0 ? or logic ? 1 ?. for applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ? 0 ? or logic ? 1 ? before normal device operation can proceed. 2.2 serial data (sda) this is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open drain terminal. therefore, the sda bus requires a pull-up resistor to v cc (typical 10 k for 100 khz, 2 k for 400khz and 1mhz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. 2.4 write-protect (wp) this pin must be connected to either v ss or v cc . if tied to v ss , write operations are enabled. if tied to v cc , write operations are inhibited but read operations are not affected. 3.0 functional description the 24xx128 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions while the 24xx128 works as a slave. both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. name 8-pin pdip 8-pin soic 8-pin tssop 8-pin msop 8-pin dfn function a0 1 1 1 ? 1 user configurable chip select a1 2 2 2 ? 2 user configurable chip select (nc) ? ? ? 1, 2 ? not connected a2 3 3 3 3 3 user configurable chip select v ss 4 4 4 4 4 ground sda 5 5 5 5 5 serial data scl 6 6 6 6 6 serial clock (nc) ? ? ? ? ? not connected wp 7 7 7 7 7 write-protect input v cc 8 8 8 8 8 +1.7v to 5.5v (24aa128) +2.5v to 5.5v (24lc128) +1.7v to 5.5v (24fc128) 24aa128/24lc128/24fc128 ds21191p-page 6 ? 2007 microchip technology inc. 4.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line, while the clock (scl) is high, determines a stop condition. all operations must end with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx128) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus figure 4-2: acknowledge timing note: the 24xx128 does not generate any acknowledge bits if an internal programming cycle is in progress. address or acknowledge valid data allowed to change stop condition start condition scl sda (a) (b) (d) (d) (c) (a) scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point, allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter sda acknowledge bit data from transmitter ? 2007 microchip technology inc. ds21191p-page 7 24aa128/24lc128/24fc128 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a 4-bit control code. for the 24xx128, this is set as ? 1010 ? binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24xx128 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. these bits are, in effect, the three most significant bits of the word address. for the msop package, the a0 and a1 pins are not connected. during device addressing, the a0 and a1 chip select bits (figures 5-1 and 5-2) should be set to ? 0 ?. only two 24xx128 msop packages can be connected to the same bus. the last bit of the control byte defines the operation to be performed. when set to a one, a read operation is selected. when set to a zero, a write operation is selected. the next two bytes received define the address of the first data byte (figure 5-2). because only a13?a0 are used, the upper two address bits are ?don?t care? bits. the upper address bits are transferred first, followed by the less significant bits. following the start condition, the 24xx128 monitors the sda bus checking the device type identifier being transmitted. upon receiving a ? 1010 ? code and appropriate device select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24xx128 will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1 and a0 can be used to expand the contiguous address space for up to 1 mbit by adding up to eight 24xx128 devices on the same bus. in this case, software can use a0 of the control byte as address bit a14; a1 as address bit a15; and a2 as address bit a16. it is not possible to sequentially read across device boundaries. for the msop package, up to two 24xx128 devices can be added for up to 256 kbit of address space. in this case, software can use a2 of the control byte as address bit a16. bits a0 (a14) and a1 (a15) of the control byte must always be set to logic ? 0 ? for the msop. figure 5-2: address sequence bit assignments 1010 a2 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit 1010 a 2 a 1 a 0 r/w xx a 11 a 10 a 9 a 7 a 0 a 8 ?????? a 12 control byte address high byte address low byte control code chip select bits x = ?don?t care? bit a 13 24aa128/24lc128/24fc128 ds21191p-page 8 ? 2007 microchip technology inc. 6.0 write operations 6.1 byte write following the start condition from the master, the control code (four bits), the chip select (three bits) and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx128. the next byte is the least significant address byte. after receiving another acknowledge signal from the 24xx128, the master device will transmit the data word to be written into the addressed memory location. the 24xx128 acknowl- edges again and the master generates a stop condition. this initiates the internal write cycle and during this time, the 24xx128 will not generate acknowledge signals (figure 6-1). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device will immediately accept a new command. after a byte write command, the internal address counter will point to the address location following the one that was just written. 6.2 page write the write control byte, word address, and the first data byte are transmitted to the 24xx128 in much the same way as in a byte write. the exception is that instead of generating a stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a stop condition. upon receipt of each word, the six lower address pointer bits are internally incremented by ? 1 ?. if the master should transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be over- written. as with the byte write operation, once the stop condition is received, an internal write cycle will begin (figure 6-2). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. 6.3 write protection the wp pin allows the user to write-protect the entire array (0000-3fff) when the pin is tied to v cc . if tied to v ss the write protection is disabled. the wp pin is sampled at the stop bit for every write command (figure 1-1). toggling the wp pin after the stop bit will have no effect on the execution of the write cycle. figure 6-1: byte write figure 6-2: page write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size ? 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (over- writing data previously stored there), instead of being written to the next page, as might be expected. it is, therefore, necessary for the applica- tion software to prevent page write operations that would attempt to cross a page boundary. xx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data s t o p a c k a c k a c k a c k x = ?don?t care? bit s 1010 0 a 2 a 1 a 0 p xx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data byte 0 s t o p a c k a c k a c k a c k data byte 63 a c k x = ?don?t care? bit s 1010 0 a 2 a 1 a 0 p ? 2007 microchip technology inc. ds21191p-page 9 24aa128/24lc128/24fc128 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition, followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, the start bit and control byte must be resent. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes 24aa128/24lc128/24fc128 ds21191p-page 10 ? 2007 microchip technology inc. 8.0 read operation read operations are initiated in much the same way as write operations with the exception that the r/w bit of the control byte is set to ? 1 ?. there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24xx128 contains an address counter that main- tains the address of the last word accessed, internally incremented by ? 1 ?. therefore, if the previous read access was to address ? n ? ( n is any legal address), the next current address read operation would access data from address n + 1 . upon receipt of the control byte with r/w bit set to ? 1 ?, the 24xx128 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24xx128 discontinues transmission (figure 8-1). figure 8-1: current address read 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 24xx128 as part of a write operation (r/w bit set to ? 0 ? ). once the word address is sent, the master gener- ates a start condition following the acknowledge. this terminates the write operation, but not before the inter- nal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a ? 1 ?. the 24xx128 will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition, which causes the 24xx128 to discontinue transmission (figure 8-2). after a random read command, the internal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24xx128 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24xx128 to transmit the next sequentially addressed 8-bit word (figure 8-3). following the final byte transmitted to the master, the master will not generate an acknowledge but will generate a stop condition. to provide sequential reads, the 24xx128 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 3fff to address 0000 if the master acknowledges the byte received from the array address 3fff. figure 8-2: random read figure 8-3: sequential read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00 aaa 1 byte 210 xx bus activity master sda line bus activity a c k n o a c k a c k a c k a c k s t o p s t a r t control byte address high byte address low byte control byte data byte s t a r t x = ?don?t care? bit s 1010 aaa 0 210 s 1010 aaa 1 210 p bus activity master sda line bus activity control byte data (n) data (n + 1) data (n + 2) data (n + x ) n o a c k a c k a c k a c k a c k s t o p p ? 2007 microchip technology inc. ds21191p-page 11 24aa128/24lc128/24fc128 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead tssop example: 8-lead soic (3.90 mm) example: xxxxxxxt xxxxyyww nnn xxxx tyww nnn 8-lead soic (5.28 mm) example: 24lc128 0510017 i/sm 24aa128 i/p 017 0510 xxxxxxxx yywwnnn t/xxxxxx 24lc128i sn 0510 017 4lc i510 017 3 e 3 e 3 e 24aa128/24lc128/24fc128 ds21191p-page 12 ? 2007 microchip technology inc. package marking information (continued) 8-lead msop example: xxxxxt ywwnnn 4l128i 051017 8-lead dfn-s example : xxxxxxx t/xxxxx yyww 24lc128 i/mf 0510 017 nnn first line marking codes part no. tssop package codes msop package codes 24aa128 4ac 4a128t 24lc128 4lc 4l128t 24fc128 4fc 4f128t * standard device marking consists of microchip part number, year code, week code, and traceability code. for device marking beyond this, certain price adders apply. please check with your microchip sales office. legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e ? 2007 microchip technology inc. ds21191p-page 13 24aa128/24lc128/24fc128 8-lead plastic dual in-line (p or pa) ? 300 mil body [pdip] n otes: 1 . pin 1 visual index feature may vary, but must be located with the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 n e1 note 1 d 12 3 a a1 a2 l b1 b e e e b c microchip technology drawing c04-018 b 24aa128/24lc128/24fc128 ds21191p-page 14 ? 2007 microchip technology inc. 8-lead plastic small outline (sn or oa) ? narrow, 3.90 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a ? ? 1.75 molded package thickness a2 1.25 ? ? standoff a1 0.10 ? 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 4.90 bsc chamfer (optional) h 0.25 ? 0.50 foot length l 0.40 ? 1.27 footprint l1 1.04 ref foot angle 0 ? 8 lead thickness c 0.17 ? 0.25 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h microchip technology drawing c04-057 b ? 2007 microchip technology inc. ds21191p-page 15 24aa128/24lc128/24fc128 8-lead plastic small outline (sm) ? medium, 5.28 mm body [soij] n otes: 1 . soij, jeita/eiaj standard, formerly called soic. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a 1.77 ? 2.03 molded package thickness a2 1.75 ? 1.98 standoff a1 0.05 ? 0.25 overall width e 7.62 ? 8.26 molded package width e1 5.11 ? 5.38 overall length d 5.13 ? 5.33 foot length l 0.51 ? 0.76 foot angle 0 ? 8 lead thickness c 0.15 ? 0.25 lead width b 0.36 ? 0.51 mold draft angle top ? ? 15 mold draft angle bottom ? ? 15 l c a2 a1 a b 12 e e e1 n d microchip technology drawing c04-056 b 24aa128/24lc128/24fc128 ds21191p-page 16 ? 2007 microchip technology inc. 8-lead plastic thin shrink small outline (st) ? 4.4 mm body [tssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.65 bsc overall height a ? ? 1.20 molded package thickness a2 0.80 1.00 1.05 standoff a1 0.05 ? 0.15 overall width e 6.40 bsc molded package width e1 4.30 4.40 4.50 molded package length d 2.90 3.00 3.10 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 ? 8 lead thickness c 0.09 ? 0.20 lead width b 0.19 ? 0.30 d n e e1 note 1 12 b e c a a1 a2 l1 l microchip technology drawing c04-086 b ? 2007 microchip technology inc. ds21191p-page 17 24aa128/24lc128/24fc128 8-lead plastic micro small outline package (ms or ua) [msop] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.65 bsc overall height a ? ? 1.10 molded package thickness a2 0.75 0.85 0.95 standoff a1 0.00 ? 0.15 overall width e 4.90 bsc molded package width e1 3.00 bsc overall length d 3.00 bsc foot length l 0.40 0.60 0.80 footprint l1 0.95 ref foot angle 0 ? 8 lead thickness c 0.08 ? 0.23 lead width b 0.22 ? 0.40 d n e e1 note 1 1 2 e b a a1 a2 c l1 l microchip technology drawing c04-111 b 24aa128/24lc128/24fc128 ds21191p-page 18 ? 2007 microchip technology inc. 8-lead plastic dual flat, no lead package (mf) ? 6x5 mm body [dfn-s] punch singulated notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a ? 0.85 1.00 molded package thickness a2 ? 0.65 0.80 standoff a1 0.00 0.01 0.05 base thickness a3 0.20 ref overall length d 4.92 bsc molded package length d1 4.67 bsc exposed pad length d2 3.85 4.00 4.15 overall width e 5.99 bsc molded package width e1 5.74 bsc exposed pad width e2 2.16 2.31 2.46 contact width b 0.35 0.40 0.47 contact length l 0.50 0.60 0.75 contact-to-exposed pad k 0.20 ? ? model draft angle top ? ? 12 note 2 a 3 a2 a1 a note 1 note 1 exposed pad bottom view 1 2 d2 2 1 e2 k l n e b e e1 d d1 n top view microchip technology drawing c04-113 b ? 2007 microchip technology inc. ds21191p-page 19 24aa128/24lc128/24fc128 appendix a: revision history revision l corrections to section 1.0, electrical characteristics. revision m added 1.8v 400 khz option for 24fc128. revision n revised sections 2.1, 2.4 and 6.3. removed 14-lead tssop package. revision p changed 1.8v to 1.7v throughout document; revised features section; replaced package drawings; revised product id section. 24aa128/24lc128/24fc128 ds21191p-page 20 ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. ds21191p-page 21 24aa128/24lc128/24fc128 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com 24aa128/24lc128/24fc128 ds21191p-page 22 ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21191p 24aa128/24lc128/24fc128 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2007 microchip technology inc. ds21191p-page23 24aa128/24lc128/24fc128 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: 24aa128: 128 kbit 1.7v i 2 c serial eeprom 24aa128t: 128 kbit 1.7v i 2 c serial eeprom (tape and reel) 24lc128: 128 kbit 2.5v i 2 c serial eeprom 24lc128t: 128 kbit 2.5v i 2 c serial eeprom (tape and reel) 24fc128: 128 kbit high speed i 2 c serial eeprom 24fc128t: 128 kbit high speed i 2 c serial eeprom (tape and reel) temperature range: i= -40 c to +85 c e= -40 c to +125 c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (3.90 mm body), 8-lead sm = plastic soic (5.28 mm body), 8-lead st = plastic tssop (4.4 mm), 8-lead mf = dual, flat, no lead (dfn)(6x5 mm body), 8-lead ms = plastic micro small outline (msop), 8-lead examples: a) 24aa128-i/p: industrial temp., 1.7v, pdip package. b) 24aa128t-i/sn: tape and reel, industrial temp., 1.7v, soic package. c) 24aa128-i/st: industrial temp., 1.7v, tssop package. d) 24aa128-i/ms: industrial temp., 1.7v, msop package. e) 24lc128-e/p: extended temp., 2.5v, pdip package. f) 24lc128-i/sn: industrial temp., 2.5v, soic package. g) 24lc128t-i/sn: tape and reel, industrial temp., 2.5v, soic package. h) 24lc128-i/ms: industrial temp., 2.5v, msop package. i) 24fc128-i/p: industrial temp., 1.7v, high speed, pdip package. j) 24fc128-i/sn: industrial temp., 1.7v, high speed, soic package. k) 24fc128t-i/sn: tape and reel, industrial temp., 1.7v, high speed, soic package 24aa128/24lc128/24fc128 ds21191p-page24 ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. ds21191p-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, ps logo, seeval, smartsensor and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds21191p-page 26 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06 |
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